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00009 #ifndef _SLOT_PXA27X_H
00010 #define _SLOT_PXA27X_H
00011
00012 #define PXA27X_MMC_MMCLK_BASE_FREQ 19500000
00013 #define PXA27X_MMC_FIFO_SIZE 32
00014
00015 #define STOP_CLOCK (1 << 0)
00016 #define START_CLOCK (2 << 0)
00017
00018 #define STAT_END_CMD_RES (1 << 13)
00019 #define STAT_PRG_DONE (1 << 12)
00020 #define STAT_DATA_TRAN_DONE (1 << 11)
00021 #define STAT_CLK_EN (1 << 8)
00022 #define STAT_RECV_FIFO_FULL (1 << 7)
00023 #define STAT_XMIT_FIFO_EMPTY (1 << 6)
00024 #define STAT_RES_CRC_ERR (1 << 5)
00025 #define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
00026 #define STAT_CRC_READ_ERROR (1 << 3)
00027 #define STAT_CRC_WRITE_ERROR (1 << 2)
00028 #define STAT_TIME_OUT_RESPONSE (1 << 1)
00029 #define STAT_READ_TIME_OUT (1 << 0)
00030
00031 #define SPI_CS_ADDRESS (1 << 3)
00032 #define SPI_CS_EN (1 << 2)
00033 #define CRC_ON (1 << 1)
00034 #define SPI_EN (1 << 0)
00035
00036 #define CMDAT_SDIO_INT_EN (1 << 11)
00037 #define CMDAT_STOP_TRAN (1 << 10)
00038 #define CMDAT_SD_4DAT (1 << 8)
00039 #define CMDAT_DMAEN (1 << 7)
00040 #define CMDAT_INIT (1 << 6)
00041 #define CMDAT_BUSY (1 << 5)
00042 #define CMDAT_STREAM (1 << 4)
00043 #define CMDAT_WRITE (1 << 3)
00044 #define CMDAT_DATAEN (1 << 2)
00045 #define CMDAT_RESP_NONE (0 << 0)
00046 #define CMDAT_RESP_SHORT (1 << 0)
00047 #define CMDAT_RESP_R2 (2 << 0)
00048 #define CMDAT_RESP_R3 (3 << 0)
00049
00050 #define RDTO_MAX 0xffff
00051
00052 #define BUF_PART_FULL (1 << 0)
00053
00054 #define SDIO_SUSPEND_ACK (1 << 12)
00055 #define SDIO_INT (1 << 11)
00056 #define RD_STALLED (1 << 10)
00057 #define RES_ERR (1 << 9)
00058 #define DAT_ERR (1 << 8)
00059 #define TINT (1 << 7)
00060 #define TXFIFO_WR_REQ (1 << 6)
00061 #define RXFIFO_RD_REQ (1 << 5)
00062 #define CLK_IS_OFF (1 << 4)
00063 #define STOP_CMD (1 << 3)
00064 #define END_CMD_RES (1 << 2)
00065 #define PRG_DONE (1 << 1)
00066 #define DATA_TRAN_DONE (1 << 0)
00067
00068 #define MMC_I_MASK_ALL 0x00001fff
00069
00070 #endif