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00009 #ifndef _SLOT_SHC_H
00010 #define _SLOT_SHC_H
00011
00012 #include <oska/io.h>
00013
00014
00015 #define SHC_SYSTEM_ADDRESS 0x00
00016
00017 #define SHC_BLOCK_SIZE 0x04
00018 # define SHC_BLOCK_SIZE_DMA_BOUNDARY_4K (0x0 << 12)
00019 # define SHC_BLOCK_SIZE_DMA_BOUNDARY_512K (0x7 << 12)
00020
00021 #define SHC_BLOCK_COUNT 0x06
00022 #define SHC_ARG 0x08
00023
00024 #define SHC_TRANSFER_MODE 0x0c
00025 # define SHC_TRANSFER_MODE_DMA_EN 0x0001
00026 # define SHC_TRANSFER_MODE_BLK_CNT_EN 0x0002
00027 # define SHC_TRANSFER_MODE_AUTO_CMD12_EN 0x0004
00028 # define SHC_TRANSFER_MODE_DATA_READ 0x0010
00029 # define SHC_TRANSFER_MODE_MULTI_BLK 0x0020
00030
00031 #define SHC_CMD 0x0e
00032 # define SHC_CMD_RESP_NONE 0x0000
00033 # define SHC_CMD_RESP_136 0x0001
00034 # define SHC_CMD_RESP_48 0x0002
00035 # define SHC_CMD_RESP_48B 0x0003
00036 # define SHC_CMD_RESP_CRC_CHK 0x0008
00037 # define SHC_CMD_RESP_IDX_CHK 0x0010
00038 # define SHC_CMD_DATA_PRESENT 0x0020
00039 # define SHC_CMD_TYPE_ABORT (0x3 << 6)
00040 # define SHC_CMD_IDX(c) ((c) << 8)
00041
00042 #define SHC_RESPONSE_0_31 0x10
00043
00044 #define SHC_BUFFER_DATA_PORT 0x20
00045
00046 #define SHC_PRESENT_STATE 0x24
00047 # define SHC_PRESENT_STATE_CMD_INHIBIT 0x00000001
00048 # define SHC_PRESENT_STATE_DAT_INHIBIT 0x00000002
00049 # define SHC_PRESENT_STATE_CARD_PRESENT 0x00010000
00050
00051 #define SHC_HOST_CTRL 0x28
00052 # define SHC_HOST_CTRL_LED_ON 0x01
00053 # define SHC_HOST_CTRL_4BIT 0x02
00054 # define SHC_HOST_CTRL_HIGH_SPD_EN 0x04
00055
00056
00057 #define SHC_PWR_CTRL 0x29
00058 # define SHC_PWR_CTRL_3V3 0x0e
00059 # define SHC_PWR_CTRL_ON 0x01
00060
00061 #define SHC_BLOCK_GAP_CTRL 0x2a
00062 #define SHC_WAKEUP_CTRL 0x2b
00063
00064 #define SHC_CLOCK_CTRL 0x2c
00065 # define SHC_CLOCK_CTRL_INT_CLK_EN 0x01
00066 # define SHC_CLOCK_CTRL_INT_CLK_STABLE 0x02
00067 # define SHC_CLOCK_CTRL_SD_CLK_EN 0x04
00068 # define SHC_CLOCK_CTRL_DIV(d) (((d) >> 1) << 8)
00069
00070 #define SHC_TIMEOUT_CTRL 0x2e
00071 # define SHC_TIMEOUT_CTRL_MAX 0x0e
00072
00073 #define SHC_SOFTWARE_RST 0x2f
00074 # define SHC_SOFTWARE_RST_ALL 0x01
00075 # define SHC_SOFTWARE_RST_CMD 0x02
00076 # define SHC_SOFTWARE_RST_DAT 0x04
00077
00078 #define SHC_INT_STATUS 0x30
00079 #define SHC_INT_STATUS_EN 0x34
00080 #define SHC_INT_SIGNAL_EN 0x38
00081 # define SHC_INT_CMD_COMPLETE 0x00000001
00082 # define SHC_INT_TRANSFER_COMPLETE 0x00000002
00083 # define SHC_INT_BLOCK_GAP 0x00000004
00084 # define SHC_INT_DMA 0x00000008
00085 # define SHC_INT_WR_BUF_RDY 0x00000010
00086 # define SHC_INT_RD_BUF_RDY 0x00000020
00087 # define SHC_INT_CARD_INSERTED 0x00000040
00088 # define SHC_INT_CARD_REMOVED 0x00000080
00089 # define SHC_INT_CARD_INT 0x00000100
00090 # define SHC_INT_ERR_ANY 0x00008000
00091 # define SHC_INT_ERR_CMD_TIMEOUT 0x00010000
00092 # define SHC_INT_ERR_CMD_CRC 0x00020000
00093 # define SHC_INT_ERR_CMD_ENDBIT 0x00040000
00094 # define SHC_INT_ERR_CMD_INDEX 0x00080000
00095 # define SHC_INT_ERR_CMD_ALL 0x000f0000
00096 # define SHC_INT_ERR_DAT_TIMEOUT 0x00100000
00097 # define SHC_INT_ERR_DAT_CRC 0x00200000
00098 # define SHC_INT_ERR_DAT_ENDBIT 0x00400000
00099 # define SHC_INT_ERR_DAT_ALL 0x00700000
00100 # define SHC_INT_ERR_CURRENT_LIMIT 0x00800000
00101 # define SHC_INT_ERR_AUTO_CMD12 0x01000000
00102 # define SHC_INT_ERR_ALL 0x01ff0000
00103 # define SHC_INT_ALL 0x01ff81ff
00104
00105 #define SHC_AUTO_CMD12_STATUS 0x3c
00106
00107 #define SHC_CAPS 0x40
00108 # define SHC_CAPS_TO_BASE_CLK_FREQ(c) (((c) & 0x00003f00) >> 8)
00109 # define SHC_CAPS_PWR_3V3 (1 << 24)
00110
00111 #define SHC_MAX_CURRENT_CAPS 0x4c
00112
00113
00114 #define PCI_SHC_SLOT_INFO 0x40
00115
00116
00117 #define SHC_RESET_TIMEOUT_MS 100
00118
00119
00120 #define SHC_INT_CLK_STABLE_TIMEOUT_MS 100
00121
00122
00123
00124
00125
00126
00127 #define SLOT_SHC_QUIRK_NO_VOLTAGE_CAPS (1 << 0)
00128
00129
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00132
00133
00134
00135 #define SLOT_SHC_QUIRK_R5B_BROKEN (1 << 1)
00136
00137
00138
00139
00140
00141
00142 #define SLOT_SHC_QUIRK_HIGH_SPD_BROKEN (1 << 2)
00143
00144
00145
00146
00147
00148
00149 #define SLOT_SHC_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 3)
00150
00151
00152
00153
00154
00155
00156
00157 #define SHC_QUIRK_DMA_NEEDS_DWORD_ALIGNED_ADDR (1 << 4)
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00164
00165 #define SHC_QUIRK_RESET_EVERY_CMD_COMPLETE (1 << 5)
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00169
00170
00171 #define SHC_QUIRK_JMICRON_JMB38X (1 << 6)
00172
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00181
00182
00183 #define SHC_QUIRK_DMA_NEEDS_DWORD_ALIGNED_LEN (1 << 7)
00184
00185 struct sdioemb_shc {
00186 struct sdioemb_slot *slot;
00187 void (*enable_int)(struct sdioemb_slot *slot, uint32_t ints);
00188 void (*disable_int)(struct sdioemb_slot *slot, uint32_t ints);
00189 void (*cmd_complete)(struct sdioemb_slot *slot, struct sdioemb_cmd *cmd);
00190 uint32_t quirks;
00191 os_io_mem_t addr;
00192
00193 os_spinlock_t lock;
00194 os_timer_t lockup_timer;
00195 uint32_t base_clk;
00196 struct sdioemb_cmd *current_cmd;
00197 uint8_t *data;
00198 size_t remaining;
00199 size_t block_size;
00200 };
00201
00202 void sdioemb_shc_init(struct sdioemb_shc *shc);
00203 void sdioemb_shc_clean_up(struct sdioemb_shc *shc);
00204
00205 int sdioemb_shc_start(struct sdioemb_shc *shc);
00206 void sdioemb_shc_stop(struct sdioemb_shc *shc);
00207
00208 bool sdioemb_shc_isr(struct sdioemb_shc *shc, uint32_t *int_stat);
00209 void sdioemb_shc_dsr(struct sdioemb_shc *shc, uint32_t int_stat);
00210
00211 int sdioemb_shc_set_bus_freq(struct sdioemb_shc *shc, int clk);
00212 int sdioemb_shc_set_bus_width(struct sdioemb_shc *shc, int bus_width);
00213 int sdioemb_shc_start_cmd(struct sdioemb_shc *shc, struct sdioemb_cmd *cmd,
00214 bool use_dma, uint64_t dma_addr);
00215 int sdioemb_shc_card_present(struct sdioemb_shc *shc);
00216 int sdioemb_shc_card_power(struct sdioemb_shc *shc, enum sdioemb_power power);
00217 void sdioemb_shc_enable_card_int(struct sdioemb_shc *shc);
00218 void sdioemb_shc_disable_card_int(struct sdioemb_shc *shc);
00219 int sdioemb_shc_hard_reset(struct sdioemb_shc *shc);
00220
00221 void sdioemb_shc_show_quirks(struct sdioemb_shc *shc);
00222
00223 #endif